Bring digital to every person, home and organization for a fully connected world.
Bring digital to every person, home and organization for a fully connected world.
Responsibility:
1.Conduct research on DFT (Design for Test) methodologies for digital logic chips, focusing on defect mechanisms, fault simulation, and failure analysis.
2.Develop DFT testing methodologies for 3DIC chips, and conduct research on defect mechanisms, fault simulation, and failure analysis related to 3DIC and IO interconnects.
3.Explore DFT testing approaches for Memory, emerging NVM (Non-Volatile Memory), and analog IP, with research experience in memory and analog defect mechanisms, fault models, and failure analysis.
4.Responsible for system-level, end-to-end DFX (Design for Excellence) architecture and test implementation, with in-depth understanding of chip lifecycle management concepts and methodologies.
Requirenment:
1. Technical Expertise Requirements
(1) Familiar with DFT technologies such as MBIST, SCAN, and ATPG, as well as semiconductor manufacturing processes and device structures.
(2) Knowledge of digital and analog circuit failure mechanisms, fault modeling, and test algorithms.
(3) Research experience in digital circuit defect mechanisms, fault simulation, and failure analysis.
(4) Research experience in 3DIC and IO interconnect defects, fault simulation, and failure analysis.
(5) Research experience related to memory or analog circuit defect modeling, simulation, and failure analysis.
(6) Experience in system-level DFX implementation, protection strategies, and failure localization techniques.
2. Educational Requirements
(1) Master’s degree or above
(2) Majors in Electronics, Microelectronics, Communications, Automation, Semiconductor Engineering, Mathematics, Physics, Chemistry, or related fields.
3. Work Experience
5–10 years of relevant experience.
Responsibility:
1.Develop high-speed clock bus solutions and drive technology evolution within and between dies to meet extreme PPA (Power, Performance, Area) requirements of product projects.
2.Conduct physical design methodology research and technology evolution to build physical design competitiveness in multi-die scenarios such as 2.5D and 3D (Chiplet, 3DIC), including but not limited to:
(1)Cross-die floorplan, clock, interconnect/bus, power delivery, and thermal management
(2)Development and implementation of cross-die physical design signoff methodologies
(3)Establishment of 3DIC reliability analysis methodologies
3.Based on physical design, lead or participate in end-to-end STCO/DTCO efforts, driving the development and evolution of Design Methodology tools related to physical design.
Requirenment:
1. Technical Expertise Requirements
(1) Proficient in back-end physical implementation, with hands-on experience in high-speed physical design flows and tools; participated in large-scale chip physical implementation and physical verification projects.
(2) Proven experience in the planning or delivery of high-speed clock buses or Chiplet/3DIC designs.
(3) Familiar with characteristics of mainstream semiconductor processes, with process analysis capabilities.
(4) Capable of translating market requirements into product planning and overall chip architecture definition.
(5) Skilled in physical architecture planning, physical design, and signoff for Chiplet/3DIC systems.
2. Educational Requirements
(1) Master’s degree or above
(2) Major in Electronics, Communications, Computer Science, Mathematics, Automation, Materials Science, Physics, or other related fields.
3. Work Experience
5–10 years of relevant experience
Location: Leuven, Belgium – Huawei European Research Institute
About Huawei: At Huawei, we believe in enriching people’s lives through communication and technology. By leveraging our expertise in the telecom sector, we help bridge the digital divide, offering everyone the chance to join the Information Age —regardless of where they live.
Our European Research Institute (ERI), based in Leuven, is home to 18 sites across 12 countries, where we conduct cutting-edge research in fields like AI, 5G, cloud computing, and more! Our goal? To lead the world in innovation and deliver next-gen solutions across the globe .
We’re looking for YOU – a 3D Integration Program Director with a passion for research and development (R&D) to help us push the boundaries of telecom, network technologies, and 3D engineering.
Responsibilities: Lead high-impact projects in AI/CPU, networking, and other future-driven areas!
Design and implement a competitive 3D engineering architecture based on cutting-edge application scenarios.
⚙️ Decompose complex engineering structures into actionable plans and take charge of risk management to turn technical ideas into commercial breakthroughs.
Drive innovative research and engage in global knowledge exchange with industry leaders on 3D technologies.
Bring your expertise in 3D integration (think 3D IC, 3D packaging, chip-to-chip technologies) to shape the future of telecommunications, AI, and 5G!
Required Skills & Qualifications: PhD in Engineering, Materials Science, or a related field – your expertise is key!
Over 10 years of experience in 3D integration, semiconductor manufacturing, or advanced materials!
Deep knowledge of 3D IC technologies, heterogeneous integration, MEMS, and chip stacking.
️ Strong communication skills and a collaborative mindset – work with brilliant minds across multiple teams.
Excellent analytical abilities and experience in leading complex projects.
Why Huawei? Work at the forefront of innovation in telecom, AI, 5G, and networking with global experts!
Join a company committed to creating a digital future through sustainable technologies.
Be part of Huawei’s R&D community and collaborate across borders, driving advancements that shape next-gen solutions!
If you’re a PhD-level expert in 3D integration and ready to make an impact on the future of tech, come join us at Huawei to lead transformative projects in the world of telecom and networking!
#3DIntegration #Telecom #AI #R&D #5G #Semiconductors #EngineeringJobs #Innovation #PhDJobs #HeterogeneousIntegration #MEMS #HuaweiCareers #TechJobs #Leuven #Networking #ResearchAndDevelopment #TechInnovation #FutureOfTech #JobOpportunity #EngineeringCareers #DigitalTransformation
Position: 3GPP RAN Plenary Standards Delegate
Position Responsibilities:
Position Requirements:
Position: 3GPP RAN1 Standards Delegate
Position Responsibilities:
Position Requirements:
Job responsibility:
1. Continuously break through advanced frameworks and innovative technologies for software IDEs, focusing on new business scenarios and developer ecosystems, centered on developer experience and productivity, making software development simpler, more efficient, and smarter, significantly enhancing programming experience and software development efficiency, and supporting the construction of Huawei's developer ecosystem;
2. Explore the evolutionary form of the next-generation intelligent IDE, enhance the multimodal intelligent development interaction of the IDE and the distributed multi-scenario development experience, and build intelligent development capabilities in the AI era (AI4SE);
3. Be responsible for the research and breakthrough of intelligent development capabilities in the new developer ecosystem, explore and solve the challenging topics of AI-assisted intelligent research and development in the new ecosystem, and achieve the application and landing of key technical competitiveness in products and ecosystems;
4. Collaborate with top global universities and laboratories on technical cooperation, participate in industry trend insights, key challenge analysis, solution architecture design, and implementation, and build the core competitiveness of software IDEs.
Job requirement:
1. Candidates with several years of experience in the field of software engineering and AIGC, and who have led the design and development of well-known mature software engineering toolchain products in the industry are preferred (such as Cursor, VSCode, IDEA, Copilot, etc.);
2. Familiar with theories and technologies in the AI and big data fields: familiar with the basic theories and algorithms of natural language processing, machine learning, and big data analysis, with relevant project experience in data mining, information retrieval, semantic understanding, recommendation systems, and have experience in designing next-generation development tools, such as experience in implementing code generation capabilities with large models is preferred;
3. Possess a strong insight and keen sense for cutting-edge industry technologies, able to continuously focus on and follow the forefront technologies in the fields of software engineering and AIGC, and be good at innovation, able to propose personal ideas and put them into practice;
4. Have excellent execution, communication, and coordination skills, able to collaborate with cross-team resources to promote the rapid implementation of product solution design requirements;
5. Priority will be given to those with experience in technical management in large teams.
Location: EU-SID CBG Dept, and be located at Huawei European Research Centers (Negotiable)
Job Overview:
We are looking for a Wearables Standardization Engineer, who are expected to work for EU-SID CBG Standards & Industry Development Dept. in Europe. This work should cover major CBG wearables related tasks in IEC and other European industry organizations, including testing standards development, health data interoperability standards development, and testing/certification promotion.
Main Responsibilities:
Competency Requirements:
About the role:
We are seeking a technical expert in Compute domain to join Belgium Research Center. The role will work closely with global collaboration team, technology planning team and product team to define long-term and short-term technology strategy. The successful candidate will identify collaboration opportunities with leading academic scientists and innovative startups in the EU, driving next-generation business and consumer experiences in both general-purpose and AI compute domains.
Key Responsibilities：
Qualifications：
Location: Leuven, Belgium
Notice:
HUAWEI is an equal opportunities employer, also committed to serving our diverse community and welcomes applications from all. By applying to this position, you agree with our RECRUITMENT PRIVACY STATEMENT. You can read in full our recruitment privacy statement via the link below.
http://career.huawei.com/reccampportal/portal/hrd/weu_rec_all.html
About the position
We are looking for a technical expert in Compute domain to join Belgium Research Center. The role will work closely with global collaboration team, technology planning team and product team, define long term and short term technology strategy, seek for collaboration opportunities with top academic scientists and innovative start-ups in EU, , and drive the next generation business and consumer experience in both general purpose compute domain and AI compute domain.
Key Responsibilities：
Background：
Skills:
Responsibility:
1.Responsible for DTCO (Design-Technology Co-Optimization) for advanced process nodes, working with Fab, design, and product teams to define technology, identify optimization directions, improve process, and enhance PPA (Power, Performance, Area).
2.Define and optimize process knobs, identify process/design risks, and propose mitigation or optimization strategies.
3.Based on PPA targets, define device types and specifications, optimize standard cell/SRAM architectures, and deliver corresponding DRM (Design Rule Manual) requirements.
4.Identify process/design risks from OPC (Optical Proximity Correction), DFM (Design for Manufacturability), and DFR (Design for Reliability) perspectives, and propose improvements.
5.Based on PPA analysis at module-level physical design, propose SoC-level optimization strategies, including physical design flow, PDN (Power Delivery Network) design, and metal stack definition.
6.Develop benchmarking methodologies, analyze and interpret PPA data.
7.Conduct research on industry DTCO trends and competitive analysis, lead DTCO direction, and define and optimize competitive process platforms.
Requirenment:
1. Technical Expertise Requirements: In-depth understanding of DTCO (Design-Technology Co-Optimization)
(1) Experience in process integration, OPC, DFM, circuit design, integrated circuit design, FIP (e.g., standard cell and SRAM) design, device and model definition, DRM (Design Rule Manual) development, etc.
(2) Familiar with semiconductor process flow or product development, ground rules, IC design, circuit analysis, layout, RC extraction, P&R (Place and Route), and other related knowledge.
(3) Proficient in Process Design Kits (PDKs), circuit design/simulation, layout, and Design Methodology tools, with the ability to debug and solve technical issues.
(4) Knowledge of technology PPA (Power, Performance, Area) benchmarking.
2. Educational Requirements:
(1) Master’s degree or above
(2) Majors in Microelectronics, Electronics, Electrical Engineering, Materials Science, Physics, or related fields.
3. Work Experience:
5–10 years of relevant experience.
Position: EU Energy Efficiency and Environmental Regulations and Standards Expert
Background: Amid the ongoing refinement of EU energy efficiency and environmental regulations, compliance requirements for consumer electronics are undergoing progressive elevation. As the Energy Efficiency and Environmental Expert in the Standardization and Industry Development European Consumer BG Team, responsible for providing insights into European energy efficiency and environmental policies and coordinating industrial technology roadmaps, facilitating the mutual promotion of technological innovation and business practices in the process of sustainable development. By gaining in-depth insights into policy and regulatory dynamics, providing forward-looking analysis, and formulating response strategies, ensure that the company’s products comply with the latest EU energy efficiency and environmental entry standards, facilitate the smooth market entry of Consumer BG products into the European market, and continuously lead and drive Huawei’s compliance and technological innovation in the EU energy efficiency and environmental sector.
Position Responsibilities:
Position Requirements:
Huawei Belgium Research and Development Group (formally Caliopa) is a center of excellence for silicon photonics design and processing. It was initially created as a spin-off from the University of Gent and Imec in 2010 but it has been acquired by Huawei in 2013. Huawei is the global No.2 telecom solution provider and uses approximately one sixth of all photonics components produced in the world.
Huawei aims to significantly reduce the cost of these components by investing aggressively in silicon photonics research and development and implementing solutions based on this technology. Huawei Belgium R&D group is at the heart of this program. The group is located in Gent, a vibrant city in Belgium in the heart of Europe.
To strengthen our team, Caliopa is now looking for a Photonics Design Engineer.
Job responsibilities:
Requirements & Qualifications:
Experience requirements:
Language:
Attitude:
Huawei’s Belgium R&D Center offers an excellent opportunity for highly skilled : GATE DRIVER IC DESIGN EXPERTS &/or GATE DRIVER IC DESIGN SENIOR ENGINEERS.
We're seeking team players and technical leaders who get things done and share a passion for bringing new technologies to a rapidly growing market. Now is your chance to join the engineering team and develop new, world-leading and innovative products. This role empowers you to provide impactful technical contribution and innovative advice across development teams, fostering a collaborative environment where creativity, high quality and expertise thrive.
Key Responsibilities:
Contributing to the detailed definition and architecture development of gate driver.
Lead the design, simulation, and optimization of gate driver systems, ensuring high performance and reliability.
Develop system models and participates in top level simulation.
Determine design-for-test strategies to evaluate system/sub-system/block performance.
Provide guidance to layout engineers on critical analog implementation aspects, monitors progress of layouts, and closes the loop with post layout extraction and simulation.
Provide guidance to EVB board design, test plan and related test equipment usage.
Assist in preparing technical reports, presentations, and documentation for both internal and external stakeholders.
Stay up-to-date with the latest developments of gate driver and related process.
Required Qualifications:
Master’s degree or Ph.D. in Electrical Engineering.
10+ years’ experience as an analog/mixed signal IC designer (5+y for the Sr. engineer role).
Proven experience in the design and analysis of gate driver or related systems.
Proficiency with system modeling and simulation tools.
In depth knowledge of drivers, HV-technology experience, isolated communication, LDOs, ADCs, oscillators but not limited to this list.
Good understanding in state of the art IC development flow/methodologies/tools.
Strong problem-solving skills and ability to work independently and as part of a collaborative team.
Experienced in developing full chip IC from requirements engineering to tape out.
Result driven, detail oriented and determined
Continuous strive for improvement in circuits and process
Willing to relocate if applicable (office in Leuven or Ghent). No hybrid or remote working
Preferred Qualifications:
Experience in a fast-paced, product-driven R&D environment.
Published papers or patents in the field of gate driver or related technologies or equivalent industry expertise.
Have the test experience of gate driver IC or power device module
Job Overview:
We are looking for a Hardware Standardization Engineer, who are expected to work for Huawei Consumer Business Group Standards & Industry Development Department in Europe (EU-SID CBG). This work scope should cover major CBG products related to hardware standards (Smartphone, Wearables, Tables, etc.) and be involved with international standardization organizations, such as NFC Forum, Wireless Power Consortium (WPC), MIPI, and RFID/Storage/Battery/Other Hardware - related organizations. The standardization tasks include: technology insights, analysis of testing standards, interoperability development, certification, and industry promotion activities.
Main Responsibilities:
Competency Requirements:
Huawei Amsterdam Research Center is at the forefront of artificial intelligence and machine learning innovation. We are dedicated to developing cutting-edge technologies that revolutionize how people interact with information and enhance productivity across various sectors. Our team of experts is committed to pushing the boundaries of what's possible in AI, and we are looking for talented individuals to join us on this exciting journey.
We are currently seeking a highly motivated and experienced Human Resources Specialist to join our team. This role is essential in managing day-to-day HR operations, employee relations, and ensuring compliance with Dutch labor laws and regulations.
Key Responsibilities:
Qualifications:
Huawei Amsterdam Research Center is at the forefront of artificial intelligence and machine learning innovation. We are dedicated to developing cutting-edge technologies that revolutionize how people interact with information and enhance productivity across various sectors. Our team of experts is committed to pushing the boundaries of what's possible in AI, and we are looking for talented individuals to join us on this exciting journey.
Position Overview:
We are seeking a highly skilled and motivated Research Engineer to join our team, focusing on information retrieval and generative models. In this role, you will be responsible for developing, implementing, and optimizing models to enhance the accuracy and efficiency of information retrieval and the user experience of using generative models. In particular, we are interested in the multimodality scenario where the inputs are not necessarily text only. You will work closely with a team of researchers, data scientists, and engineers to create innovative solutions that leverage large-scale datasets and advanced machine learning techniques.
Key Responsibilities:
Design, implement, and optimize information retrieval models and establish a strong retrieval-augmented generation (RAG) system.
Enhance the user experience by improving LLM's reasoning capabilities and reducing the hallucinations
Conduct research on state-of-the-art methods in natural language processing (NLP), machine learning (ML), and information retrieval (IR).
Develop algorithms and techniques to improve the performance and scalability of RAG systems.
Collaborate with cross-functional teams to integrate RAG solutions into existing products and services.
Perform data collection, pre-processing, and analysis to support research and development activities.
Evaluate and benchmark the performance of RAG models using large-scale datasets.
Stay up-to-date with the latest advancements in AI, NLP, ML, and IR.
Qualifications:
Master’s or Ph.D. in Computer Science, Electrical Engineering, or a related field with a focus on NLP, ML, or IR.
Strong programming skills in Python and familiarity with machine learning frameworks such as PyTorch.
Solid understanding of deep learning architectures, including transformers, BERT, GPT, etc.
Proven track record of research excellence, demonstrated through publications in relevant conferences and journals.
Ability to work independently and as part of a collaborative team.
Excellent problem-solving skills and attention to detail.
Strong communication skills, both written and verbal.
Preferred Qualifications:
Knowledge and hands-on experience on automatic speech recognition (ASR) is a big plus.
Experience with retrieval-based models and techniques, including vector space models, BM25, or neural retrieval methods.
Familiarity with knowledge bases, information extraction, and question answering systems.
Background in software development and engineering best practices.
Description:
This is an open resume submittion channel for students who want to find an internship at Huawei.
Your submitted information will be carefully reviewed to match you with the most suitable position.
We appreciate your proactive engagement, and rest assured that all details provided will be treated confidentially and used exclusively for Huawei's internal recruitment purposes.
We look forward to receiving your application and potentially welcoming you to the Huawei team.
Contact person： yu.fu2@huawei-partners.com
Location: Leuven, Belgium
About the Role:
We are seeking a highly organized, resilient, and multilingual Executive Assistant to support a senior executive in a fast-paced environment. The ideal candidate will excel at managing complex schedules, coordinating high-priority projects, and acting as a liaison across global teams. This role demands strong stress tolerance, adaptability, and a proactive mindset to navigate dynamic business needs.
Key Responsibilities:
Requirements:
Huawei Amsterdam Research Center is at the forefront of artificial intelligence and machine learning innovation. We are dedicated to developing cutting-edge technologies that revolutionize how people interact with information and enhance productivity across various sectors. Our team of experts is committed to pushing the boundaries of what's possible in AI, and we are looking for talented individuals to join us on this exciting journey.
For our R&D Centre in Amsterdam we are looking for a Linguistic Intern to join our team.
About The Job
You'll work as an integral part of an operational team, sifting language materials against requirements to identify reportable intelligence that will be forwarded to analysts to help shape and influence their operational decision making.
As a Linguistic Intern, you will be involved into evaluating the performance of the system, annotating linguistic data and working closely with our engineering team, including managing the language data systems for NLP development. You will use your analytical mindset, strong communication skills, collaborative attitude, and personal drive to increase the performance of the system.
Responsibilities
Qualifications
Huawei Belgium Research and Development Group (formally Caliopa) is a center of excellence for silicon photonics design and processing. It was initially created as a spin-off from the University of Gent and Imec in 2010 and was acquired by Huawei in 2013. Huawei is the global No. 2 telecom solution provider and uses approximately one sixth of all photonics components produced in the world.
Huawei is continuously investing in silicon photonics research and development to generate top notch solutions based on this technology. Huawei Belgium R&D group is at the heart of this program. The group is located in Gent, a vibrant city in Belgium in the heart of Europe.
To strengthen our team, we are now looking for a Photonics Design Expert.
Job responsibilities:
Requirements & Qualifications:
Language:
Attitude:
Huawei is a leading telecom solutions provider. Through continuous customer-centric innovation, Huawei has established end-to-end advantages in Telecom Network Infrastructure, Application & Software, Professional Services and Devices. With comprehensive strengths in wireline, wireless and IP technologies, Huawei has gained a leading position in the All-IP convergence age. Its products and solutions have been deployed in over 100 countries and have served 45 of the world's top 50 telecom operators, as well as one third of the world's population.
Our Huawei R&D teams develop next generation RF transceivers, supporting 4G (LTE) and 5G systems.
Today, we're seeking team players and technical leaders who get things done and share a passion for bringing new wireless technologies to the rapidly growing mobile market. Now is your chance to join the engineering team and develop new, world-leading products.
We are offering a PRINCIPAL (RF/ANALOG/mixed-signal) IC DESIGN ENGINEER – TECHNICAL LEADER position enabling you to join the creation of the next generation mobile phone chips.
The ability to analytically reason on different circuit topologies, based on an overview of the state-of-the-art, select the right architecture and tweak the right parameters to meet stringent criteria for these circuits is your strength.
This role includes technical leadership, meaning technical hands-on expertise and excellent team skills; together with his/her teammembers, this candidate targets high and challenging standards on technical performance, product and process quality and project schedule.
You are/have:
Position Overview:
We are seeking an innovative and experienced R&D Silicon Photonics Heterogeneous Integration Expert to lead the development of advanced heterogenous integration schemes and architect solutions that push the boundaries of our Silicon Photonics platform. This role involves overseeing the integration of active photonic devices—including lasers, modulators, and photodetectors—into next-generation transceivers and other high-performance photonic systems. The ideal candidate will possess strong expertise in heterogenous integration, laser technology, and Silicon Photonics, paired with a solid foundation in project management and team leadership.
Key Responsibilities:
Qualifications:
Position Overview:
We are seeking a highly skilled and motivated R&D Engineer with expertise in new material systems and devices for our existing Silicon Photonics process platforms. The successful candidate brings key knowledge on the fabrication and integration of photonic devices incorporating specialized materials such as Lithium Niobate (LiNbO3), Barium Titanate (BaTiO3), organic materials, Silicon Germanium (SiGe) or photonic device process architecture experience of Germanium Avalanche Photodiodes (Ge APDs), SiGe photodetectors, and III-V semiconductor lasers or semiconductor optical amplifiers (SOAs). The candidate will play a key role in advancing our research and development efforts towards new ultra-high speed transceiver, integrated high speed detectors, multi-wavelength sources or neural network architectures based on our process platforms.
Key Responsibilities:
Qualifications:
This role focuses on guiding the direction and pace of industry development, safeguarding the healthy and sustainable growth of the semiconductor sector, and building strategic industry advantages. You will lead standard-setting strategies and industrial development planning aligned with company-level strategic goals.
Technology and Industry Insight:
Analyze key events, developer ecosystems, open-source ecosystems, and hot topics in the semiconductor industry to identify opportunities and risks. Deliver high-quality counter-strategies, project proposals, and authoritative insight reports.
Strategic Formulation:
Lead, participate in, or support the planning and decision-making of industry strategies across various levels (corporate, cross-BG, BU, etc.) and domains (standards, alliances, open source, developer ecosystems, academic/technical innovation, national initiatives, innovation hubs, etc.).
Strategic Execution:
Drive the execution and closed-loop management of semiconductor industry strategies, making timely adjustments or corrections based on practical feedback and evolving industry conditions.
As a core team member, participate in strategic insight, formulation, and implementation across fields such as policy, standards, industry alliances, open source, developers, academia, innovation, and ecosystem hubs.
Ensure execution of industry strategies and make timely refinements or corrections to key issues as needed.
Lead the design and planning of key industry development projects in areas including standards, alliances, open source, and developer ecosystems.
Independently lead or drive research initiatives (internal or external) on industry organizations, trends, pain points, and major national projects.
Provide high-value insights on external industry partners or competitors. Influence internal business owners (e.g., PDT leaders), mobilize resources, and support external partnership development or competition strategy.
Knowledge:
Solid knowledge of the semiconductor industry and its ecosystem
Proficiency in industry analysis and strategic planning methodologies
Understanding of industry alliance formation and operational strategies
Capabilities:
Strong strategic and industrial research capabilities
Project design and planning ability in industrial settings
Multilateral negotiation and partnership development skills
Capability to build and manage complex industry ecosystems
Experience:
8+ years of experience in the semiconductor industry
Background in AI is a plus
Education or experience in management or economics is a plus
As a strategic leader in semiconductor technology and industry planning, this role focuses on forecasting future trends and guiding long-term strategic directions. You will lead strategic topic initiatives, design high-level strategic blueprints, and drive execution, ultimately generating significant impact on the company’s mid-to-long-term business performance.
Technology and Industry Foresight:
Act as a forward-looking expert in key technology domains. Conduct in-depth research on disruptive innovations and potential paradigm shifts that may influence strategic decisions, and produce authoritative insights and recommendations.
Advanced Technology Research and Incubation:
Leverage foresight insights to identify critical future technology areas and guide business development and innovation priorities.
Strategic Program Execution:
Coordinate cross-functional teams and strategic partners to drive key initiatives, providing input for executive decision-making and ensuring alignment with the company’s strategic direction.
Monitor and analyze cutting-edge technology developments from leading semiconductor companies and academic institutions; assess trends and produce insight reports and strategic analyses. Lead the design and methodology of strategic research initiatives.
Provide advanced research frameworks and structured methodologies to support strategic topic studies, producing valuable outputs and actionable recommendations.
Present key findings to executive leadership and business owners in internal strategy review meetings (e.g., IPMT, IMT), supporting critical decision-making.
Communicate insights effectively to external stakeholders and industry influencers, helping build an ecosystem that supports the company's long-term strategy.
Knowledge:
Deep understanding of the semiconductor industry and value chain
Familiarity with industry analysis, strategy development, and consulting methodologies
Capabilities:
Strong research and foresight capabilities in the semiconductor field
Expert-level ability in strategic topic formulation and execution
Excellent communication, influence, and cross-functional collaboration skills
Experience:
8+ years of experience in the semiconductor or related high-tech industries
A background in AI is a plus
Educational or professional background in management or economics is a plus
About the job
We are seeking principle Power Management IC designers to join our team. Candidates will be asked to design innovative, high performance integrated circuits which include DC-DCs, AC-DCs, Gate-Drivers, and multi-functional power management circuits.
Job Responsibilities
Job Requirements
Job Title: Senior Device TCAD Engineer – Shaping the Future of Next-Gen Tech at Huawei ERI
Location: Leuven, Belgium (HQ of Huawei’s European Research Institute – where innovation meets waffles )
About Us:
At Huawei, we’re not just about connecting people; we’re about connecting everything. Our vision? To enrich lives through cutting-edge communication tech and bridge the digital divide like a boss. Think of us as the Avengers of telecom, but with fewer capes and more code.
Our European Research Institute (ERI) is the brainy hub of Huawei’s R&D universe, with 18 sites across 12 countries. We’re talking next-level innovation in tech, from AI to IoT , and everything in between. Based in Leuven, Belgium (aka the land of chocolate and beer ), we’re on a mission to build world-class products and solutions that make the future look like sci-fi. ✨
The Gig:
We’re on the hunt for a TCAD Wizard ♂️♀️ (aka Senior Device TCAD Engineer) to join our crew. If you eat, sleep, and breathe TCAD simulations, DTCO flows, and advanced device architectures, this is your dream job. You’ll be the maestro behind virtual process integration schemes for next-gen devices like NS, CFET, and 2D materials-based circuits. Basically, you’ll be designing the tech that powers the future. ⚡
Your Mission (Should You Choose to Accept It):
Develop TCAD/DTCO flows and decks for advanced devices like a pro. ️ Think of it as building the ultimate tech Lego set.
Optimize devices through simulations (emulation/process/device) to hit those sweet PPA goals.
Stay ahead of the curve by following industry trends, reading lit like it’s Netflix , and benchmarking state-of-the-art tech.
Travel the globe (okay, maybe just a few days) to attend international conferences and flex your tech expertise. ✨
What We’re Looking For:
PhD in Electrical Engineering, Computer Science, or something equally awesome. ✨
3+ years of hands-on experience with TCAD simulators (Synopsys, Silvaco, Global TCAD Solutions – you name it, you’ve mastered it). ️
Deep knowledge of semiconductor physics and applications. If you can explain FinFETs, GAA-NS, CFETs, and 2D materials in your sleep, you’re our person.
Understanding of CMOS process flow – because you can’t build the future without knowing the basics. ️
A hunger for learning – if you’re not geeking out over new tech, are you even a TCAD engineer?
English fluency (written and spoken) – bonus points if you can throw in some Dutch or Chinese.
Why Join Us?
Work in a distributed international team where collaboration is key (and time zones are just a minor inconvenience).
Be part of a world-class research center that’s pushing the boundaries of innovation.
Enjoy the perks of working in Leuven – because who doesn’t love waffles, beer, and a great work-life balance? ⚖️
Ready to Level Up?
If you’re ready to dive into the world of TCAD, DTCO, and next-gen devices, hit us up. Let’s build the future together – one simulation at a time. ⏳
Apply now and let’s make tech history!
P.S. Fluent in English is a must. Fluent in memes is a plus.
P.P.S. Bonus points if you can explain quantum computing using only emojis. ⚛️
Huawei is a leading telecom solutions provider. Through continuous customer-centric innovation, Huawei has established end-to-end advantages in Telecom Network Infrastructure, Application & Software, Professional Services and Devices. With comprehensive strengths in wireline, wireless and IP technologies, Huawei has gained a leading position in the All-IP convergence age. Its products and solutions have been deployed in over 100 countries and have served 45 of the world's top 50 telecom operators, as well as one third of the world's population.
Our Huawei R&D teams develop next generation RF transceivers, supporting 4G (LTE) and 5G systems.
Today, we're seeking team players and technical leaders who get things done and share a passion for bringing new wireless technologies to the rapidly growing mobile market. Now is your chance to join the engineering team and develop new, world-leading products.
Assignment Description
We are offering a long-term SENIOR DIGITAL IC DESIGN ENGINEER (FRONT-END) position enabling you to join the creation of the next generation RF chips.
The Senior Digital IC Design Engineer (Front-End) has the following responsibilities:
This role includes technical leadership, meaning technical hands-on expertise and excellent team skills; this candidate targets high and challenging standards on technical performance, product and process quality and project schedule.
Required Education and Experience:
We are offering a long term SENIOR DSP ENGINEER position enabling you to join the creation of the next generation mobile phone chips.
The Senior DSP Engineer is responsible for the definition of the ultra-high speed datapath for next generation wideband wireless standards. This involves the uses and analysis of integer upsampling as well as fractional upsampling over a wide range of input and output bandwidths. It also involves the use of compensation and calibration techniques to digitally pre-distort the signals to achieve improved transmission characteristics.
During the implementation phase, the DSP engineer might be requested to consider alternative solutions that can be implemented at higher speeds and/or lower power.
During the chip bring up and characterization phase, the DSP engineer is involved in the creation of example drivers to properly configure the datapath as well as analyzing measurement results.
After the measurement campaign, the DSP engineer can be asked to modify the datapath and/or compensation blocks for the next generation chip or chip evolution.
The ideal candidate is both very analytical, pragmatic and critical. He/she should be able to focus on details, but at the same time not forget about the bigger picture. Compromises are a part of daily life, specs and targets evolve.
The candidate can expect critical reviews and lively discussions in a team that consist of seniors with very diverse professional backgrounds but with strong analytical powers. Results as a team count; ego should not get in the way.
Clear and concise communication on status and progress is a strong plus. The Senior DSP Engineer can present the issues he/she encountered, potential solutions and workarounds as well as decide on a way forward.
Location : Leuven (BE), 100 % on site
Huawei is a leading telecom solutions provider. Through continuous customer-centric innovation, Huawei has established end-to-end advantages in Telecom Network Infrastructure, Application & Software, Professional Services and Devices. With comprehensive strengths in wireline, wireless and IP technologies, Huawei has gained a leading position in the All-IP convergence age. Its products and solutions have been deployed in over 100 countries and have served 45 of the world's top 50 telecom operators, as well as one third of the world's population.
Huawei Leuven R&D team develops next generation RF transceivers, supporting 4G (LTE) and 5G protocols.
Today, we're seeking team players who get things done and share a passion for bringing new wireless technologies to the rapidly growing mobile market. Now is your chance to join the engineering team and develop new, world-leading products.
We are offering a senior layout engineer position enabling you to join the creation of the next generation mobile phone chips.
The Senior RF IC Layout Engineer will be part of an experienced layout team. In close cooperation with his colleagues he will be in charge of the layout of high speed analog and RF circuits and he will take up a leading role in the floorplanning and optimization of the system on chip.
He is an expert user of Cadence and Mentor tool suites on nanometer RF CMOS and/or RF SOI technology.
The successful candidate will work closely with the RF designers. He/she will take into account the constraints from the designer and will go through iterations with the designer to further optimize the layout from a performance and area perspective.
RF circuit layout experience in the sub 10-Ghz range is mandatory.
The layout engineer should have a good understanding of the different circuit topologies and their constraints for the layout. implementation. Good understanding of the layout rules enables to optimize the implementation.
The senior layout engineer is also capable to perform extraction of parasitic and make the interpretation of these results in view of further optimization.
Job Overview:
We are looking for a Software Engineer who has expertise on Programming Languages and Operating Systems, and be expected to work for Europe Consumer BG Standardization and Industry Development (EU-SID CBG). This work should cover all software tasks for CBG, including programming language, web technology, AI algorithm, intelligent car connectivity, mobile application development, open source, operating system core enabling technologies, and software-related ecosystem partnership.
Main Responsibilities:
Competency Requirements:
Position: Software Standardization and Industry Development Engineer (EU-SID CBG)
Location: Huawei European Research Centers (Negotiable, Preferable in Edinburgh)
Job Overview:
We are looking for a Software Engineer who has expertise on Programming Languages and Operating Systems, and be expected to work for Europe Consumer BG Standardization and Industry Development (EU-SID CBG). This work should cover all software tasks for CBG, including programming language, web technology, AI algorithm, intelligent car connectivity, mobile application development, open source, operating system core enabling technologies, and software-related ecosystem partnership.
Main Responsibilities:
Competency Requirements:
Join Huawei R&D Belgium – Spontaneous Applications Welcome!
At Huawei R&D Belgium, we are shaping the future of next-generation connectivity, AI-driven computing, and cloud-native solutions. Our cutting-edge research spans 5G/6G, AI/ML, Digital IC Design, Photonics, RF Engineering, and Embedded Systems, making us a key innovation hub in Europe.
Didn’t find the perfect role on our website? No worries! We’re always on the lookout for top talents in Software Engineering, Data Science, AI/ML, IC Design, Cloud Computing, Cybersecurity, and beyond. Whether you're a seasoned expert or an emerging talent, we invite you to send us your spontaneous application.
At Huawei R&D Belgium, you’ll work with world-class researchers and engineers, pushing the boundaries of AI acceleration, HPC, Edge Computing, and Optical Networking. Join us in redefining chip architecture, energy-efficient systems, and ultra-low latency networks for a smarter, hyper-connected world.
Send us your CV and a short cover letter highlighting your expertise and aspirations. Let’s build the future together!
Huawei is a leading telecom solutions provider. Through continuous customer-centric innovation, Huawei has established end-to-end advantages in Telecom Network Infrastructure, Application & Software, Professional Services and Devices. With comprehensive strengths in wireline, wireless and IP technologies, Huawei has gained a leading position in the All-IP convergence age. Its products and solutions have been deployed in over 100 countries and have served 45 of the world's top 50 telecom operators, as well as one third of the world's population.
Our Huawei R&D teams develop next generation transceivers, supporting 4G (LTE), 5G and 6G systems.
Today, we're seeking team players who get things done and share a passion for bringing new wireless technologies to the rapidly growing high speed communication market. Now is your chance to join our leading R&D team and to develop state-of-the-art prototypes and products.
Job Description.
We are offering SENIOR INTEGRATED CIRCUITS DESIGN ENGINEER positions enabling you to join the creation of the next generation advanced communication chips.
The ability to analytically reason on different circuit topologies, based on an overview of the state-of-the-art, select the right architecture and tweak the right parameters to meet stringent criteria for these circuits is your strength.
The candidate will design (IC design), simulate, layout and test integrated analog, mixed-signal and/or RF circuits in advanced CMOS or SOI technologies.
He/she will also perform experimental verification and debugging, along with the integration of complex RF & Mixed Signal functions into system chips. Building accurate models based on layout extraction and 2D/3D modeling tools to match measurements with simulations is essential.
Required Education and Experience:
Location
Leuven (BE), (partially) remote during Covid situation
Key Responsibilities: As a key member of our technology planning (and innovation management) team, you will:
Education & Experience:
Required Skills & Competencies:
Employment Details:
Industry: Electronics & Semiconductors.
Location: Leuven (Belgium)
Responsibility:
1.Conduct thermal and stress modeling and simulation in 3DIC design, including but not limited to thermal conduction, thermal expansion, mechanical stress, thermo-mechanical coupling, electro-thermal coupling, and electromagnetic coupling and more multiphysics analysis.
2.Utilize numerical simulation methods for thermal and stress analysis, optimize design, and resolve potential thermal management issues.
3.Perform thermal and stress modeling with commercial simulation tools to ensure performance and reliability requirements are met; lead the optimization and iteration of in-house thermal simulation tools; edit and optimize numerical equations to improve simulation accuracy and efficiency.
4.Collaborate closely with cross-functional teams, providing technical support in thermal and stress modeling to ensure successful implementation of design solutions.
5.Continuously improve modeling methodologies and simulation workflows to enhance overall R&D efficiency.
Requirenment:
1. Technical Expertise Requirements
(1) Strong foundation in mathematics, physics, and thermodynamics, especially in heat conduction, stress analysis, and materials science.
(2) Familiarity with thermal and stress modeling methods and proficiency in numerical simulation techniques (e.g., finite element analysis).
(3) Proficient in using simulation tools such as ANSYS, COMSOL, Cadence, or similar software.
(4) Relevant experience in semiconductor 3DIC design, with the ability to understand and address thermal stress issues in semiconductor packaging and multilayer structures.
(5) Familiarity with programming languages such as Python and C++, with the capability to independently develop scripts.
(6) Prior work experience in semiconductor packaging, 3DIC design, or related fields is preferred.
2. Educational Requirements
(1) Master’s degree or above in Electrical Engineering, Physics, Mechanical Engineering, or related fields (Ph.D. preferred).
3. Work Experience
5–10 years of relevant experience.
Job Overview:
We are looking for a Wearables Standardization Engineer, who are expected to work for EU-SID CBG Standards & Industry Development Dept. in Europe. This work should cover major CBG wearables related tasks in IEC and other European industry organizations, including testing standards development, health data interoperability standards development, and testing/certification promotion.
Main Responsibilities:
Competency Requirements: